1. Field of the Invention
This invention relates to a semiconductor memory device for storing data in a capacitor, and more particularly to a semiconductor memory device capable of holding stored data even when the power supply is turned off.
2. Description of the Related Art
At present, semiconductor memories are widely used in computers, automobiles, audio systems, videotape recorders, televisions, etc.
In particular, DRAMs (Dynamic RAM) are used more widely than the other types of memories, since each of their memory cells has a simple and small-size structure consisting of a memory cell and a transistor, can be made easily, and has high reliability, especially, in operational speed. 4 Mbit DRAMs and 16 Mbit DRAMs are now available. These DRAMs, however, have the following problems:
As is shown in FIG. 1A, each memory cell of the DRAM consists of a transistor and a capacitor. Cell data "1", for example, written in the capacitor is shifted to "0" with the passing of time, since a junction leak current flows from that diffusion layer on the source side of the transistor, which is mainly connected to a storage node VN, to a substrate or a well, and the potential of the cell lowers, as is shown in FIG. 1B.
As can be understood from the above, the DRAMs are volatile memories from which data will disappear with the passing of time. Therefore, it is necessary to perform a refresh operation for reading data, which is once written in the DRAM after turn-on of the power supply, and rewriting the data within a maximum data holding time. Moreover, when the power supply is turned off, the junction is forwardly biased and the cell transistor is turned on. As a result, the cell data will be lost.
FIGS. 2A and 2B show test results obtained when a conventional 64 Kbit DRAM test device is turned off and then turned on to read cell data.
Specifically, FIG. 2A shows test results obtained when data is written into a memory cell, and read after 0.4 second standby (i.e., after the data is held 0.4 second), with the power supply kept on. The abscissa indicates the plate potential (VPL), while the ordinate indicates the bit line precharge voltage (VBL). As is evident from FIG. 2A, the cell data is held in the conventional DRAM standby system.
FIG. 2B shows test results obtained when data written in a memory cell of the same device is read therefrom after the power supply is turned off 0.4 second and again turned on. In FIG. 2B, the abscissa indicates the plate potential (VPL), and the ordinate indicates the bit line precharge voltage (VBL). FIG. 2B shows that the cell data is lost in the conventional DRAM system, whichever values the VPL and VBL have.
The FIG. 2B results occur from the fact that the plate potential lowers from Vcc/2 to 0V, and also from the fact that the internal circuit erroneously operates when the power supply is in the on and off states, which causes erroneous word line selection and accordingly word line floating when the power supply is on and off states, resulting in memory cell charge leakage so that data is lost.
For example, when the power supply is turned off in a case where the conventional plate potential is Vcc/2 and data "0" is written (i.e. a voltage Vss is written), the plate potential becomes Vss, and the storage node potential becomes -Vcc/2. Then, the transistor serving as an nMOS transfer gate is turned on, and the pn junction is forwardly biased, with the result that data "0" is lost.
FIG. 3 shows various types of semiconductor memories. An SRAM (Static RAM) is a volatile memory, which can operate at high speed as the DRAM and requires no refresh operation, and in which cell data is completely lost after the power supply is turned off.
On the other hand, an MROM (Mask ROM), an EPROM, an EEPROM, an FRAM (Ferroelectric RAM), etc. are included in a non-volatile memory in which data is not lost when the power supply is turned off. These memories are, however, not speedy in reading and writing, and further the number of write cycles is limited therein. For example, the MROM cannot rewrite data, while the EPROM, EEPROM, etc. can rewrite data 10.sup.5 times at maximum. This is because in these memories, data is written or erased by passing electrons through the gate oxide film by tunneling, etc., in other words, by destructing the memory cells in principle. The EPROM, EEPROM, etc. are not speedy in writing.
The FRAM stores data using polarization created by a ferrodielectric film employed therein. The FRAM is not excellent in film reliability and in the circuit for rewriting (it can perform about 10.sup.5 to 10.sup.11 times of write cycles).
In addition, the power voltage must be set low in order to enhance the reliability of the highly integrated memory device (DRAM, etc.) and to save its power consumption. On the contrary, the threshold voltage of the memory cell cannot be set so low in order to restrain an increase in the sub-threshold current flowing through the transistor. Accordingly, the DRAM cannot be operated at high speed if it is highly integrated.
If both the power voltage and the threshold voltage are reduced so as to make the speed of the memory device according to the speed of a CPU, etc., the leak current which occurs in the power-on state will increase exponential rate in accordance with the generations of DRAMs, as is shown in FIG. 4. The inventors of the present invention have proposed a method for reducing the amount of the leak current at the time of battery backup mode (sleep mode) or standby mode in order to elongate the life of the battery (Japanese Patent Application KOKAI No. 6-208790). However, there is no method for eliminating the occurrence of the leak current.
As explained above, in the conventional DRAMs, a high speed operation can be performed, and the number of write cycles is limitless. Actually, however, they are disadvantageous in that i) refresh operation must be performed so often even where the power supply is in the on state, that ii) cell data is lost when the power supply is once turned off, and no more exists when the power supply is again turned on, and that iii) power consumption is great because of leak current even in the standby mode or in the sleep mode. On the other hand, the other non-volatile memories are limited in the number of write cycles, and hence cannot be used for various purposes as compared with the DRAM and SRAM.